FE12.3 — USB 2.0 4-Port MTT Hub Controller (with Reverse Switch)

FE12.3 is a High Speed 4-Port Hub Controller based on the design of FE1.1s, and the product offers an additional bypass feature. With tiny footprint, it is the best choice for embedded application.

Bypass Mode

Setting FE12.3 to Bypass Mode will make the Upstream Port and Downstream Port 1 a direct line, allowing OTG connection between SOC USB HOST and external device.

Battery Charging Configuration

FE12.3 could be optionally configured to support Charging Downstream Ports as defined by USB-IF Battery Charging Specification. When enabling this feature, a USB hub could be transformed into a charging station for Universal Charging Solution-compliant battery-based portable devices.

Quality Guaranteed

The whole chip is covered by Test Scan Chain – even on high speed (480MHz) modules. Built-In-Self-Test mode exercises all high-, full-, and low-speed Analog Front End (AFE) components at the packaging and testing stages.

Product Brief for FE12.3PDF icon

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FE12.3 in WQFN-24 package Full size image.FE12.3 in WQFN-24 package

Product Specifications

Package Port Count Body Size Grade Transaction Translator
WQFN-24 4 4x4 mm Commercial Grade,
Extended Temperature Grade[*]		 Multiple

Commercial Grade: 0°C - 70°C
Extended Temperature Range: Certified for -40°C, 25°C, 85°C

Features

  • Fully compliant with Universal Serial Bus Specification Revision 2.0 (USB 2.0)
    • Upstream Facing Port supports High-Speed (480MHz) and Full-Speed (12MHz) modes
    • 4 Downstream Facing Ports support High-Speed (480MHz), Full-Speed (12MHz), and Low-Speed (1.5MHz) modes
  • Compliant with Universal Charging Solution, and USB Battery Charging Specification 1.1/1.2
  • USB Link Power Management (LPM) support
  • Integrated USB 2.0 Transceivers
  • Integrated upstream 1.5KΩ pull-up, downstream 15KΩ pull-down, and serial resistors
  • Integrated 3.3V to 1.8V regulator
  • Integrated Power-On-Reset circuit
  • Integrated 12MHz Oscillator with feedback resistor, and crystal load capacitor
  • Integrated 12MHz-to-480MHz Phase Lock Loop (PLL)
  • Integrated Portable Device detection circuitry for UCS supporting
  • Multiple Transaction Translators (MTT)
    • One TT for each downstream port
    • Alternate Interface 0 for Single-TT, and Alternate Interface 1 for Multiple-TT
    • Each TT can handle 64 periodic Start-Split transactions, 32 periodic Complete-Split transactions, and 6 non-periodic transactions
  • Automatic self-power status monitoring
    • Automatic re-enumeration when Self-Powered switching to Bus-Powered
  • Board configure options
    • Support of portable device detection mechanism for Universal Charging Solution on downstream ports
    • Bypass Mode select